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| 3.3V 168 pin Registered SDRAM Modules 64MB, 128MB, 256MB, 512MB & 1GB Densities * 168 Pin JEDEC Standard, Registered 8 Byte Dual-In-Line SDRAM Module for PC and Server main memory applications One bank 8M x 72, 16M x 72, 32M x 72 and 64M x 72 organisation two bank 32M x 72 & 128M x 72 organisation Optimized for ECC applications with very low input capacitances JEDEC standard Synchronous DRAMs (SDRAM) Performance: -8 fCK tCK tAC Clock frequency (max.) Clock cycle time (min.) Clock access time (min.) CAS latency = 3 CAS latency = 2 100 10 6 6 -8B 100 10 6 7 Units MHz ns ns ns * * * * * * Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs, outputs are LVTTL compatible Serial Presence Detect with E2PROM Utilizes 64M & 256M SDRAMs in TSOPII-54 packages with registers and PLL. The two bank module uses stacked TSOP54 packages 4096 refresh cycles every 64 ms Card Size: 133,35 mm x 38.1mm / 43.18mm x 4,00 / 6.50mm with Gold contact pads This specification largely follows the JEDEC STANDARD 21-C / Release 8 / Section 4.5.7 specification and as far as applicable - INTEL's "PC SDRAM Registered DIMM Specification" Rev.1.0 (Feb.98 and Rev.1.1 (Aug. 98). * * * * * * * Semiconductor Group 1 11.98 Preliminary Information HYS72V8200GR HYS72V16200GR HYS72V32200GR HYS72V32220GR HYS72V64200GR HYS72V128220GR Rev. 1.0/1.1 Ordering Information Type HYS72V8200GR-8 HYS72V8200GR-8B HYS72V16200GR-8 HYS72V16200GR-8B HYS72V32220GR-8 HYS72V32220GR-8B HYS72V32200GR-8 HYS72V32200GR-8B HYS72V64200GR-8 HYS72V64200GR-8B HYS72V128220GR-8 HYS72V128220GR-8B Speed Code PC100-222-620R PC100-323-620R PC100-222-620R PC100-323-620R PC100-222-620R PC100-323-620R PC100-222-620R PC100-323-620R PC100-222-620R PC100-323-620R PC100-222-620R PC100-323-620R Descriptions one bank 64 MB Reg. DIMM INTEL Rev. 1.0 one bank 128 MB Reg. DIMM INTEL Rev. 1.0 two bank 256 MB Reg. DIMM INTEL Rev. 1.1 one bank 256 MB Reg. DIMM INTEL Rev. 1.0 one bank 512 MB Reg. DIMM INTEL Rev. 1.0 two bank 1 GByte Reg. DIMM INTEL Rev. 1.1 SDRAM Technology 64 MBit 64 MBit 64 MBit (stacked) 256 MBit 256 MBit 256 MBit (stacked) Pin Names A0-A11,A12 BA0, BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0, CKE1 CLK0 - CLK3 Address Inputs Bank Selects Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input DQMB0 - DQMB7 CS0 - CS3 REGE VDD VSS SCL SDA N.C. Data Mask Chip Select Register Enable Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out No Connection Address Format: Density 64 MB 128 MB 256 MB 256 MB 512 MB 1 GB Org. 8M x 72 16M x 72 32M x 72 32M x 72 64M x 72 64M x 72 Memory Banks 1 1 2 1 1 2 SDRAMs 8M x 8 16M x 4 16M x 4 32M x 8 64M x 4 64M x 4 # of SDRAMs 9 18 36 9 18 36 # of row/bank/ column bits 12 / 2 / 9 12 / 2 / 10 12 / 2 / 10 13 / 2 / 10 13 / 2 / 11 13 / 2 / 11 Refresh 4k 4k 4k 8k 8k 8k Period 64 ms 64 ms 64 ms 64 ms 64 ms 64ms Interval 15,6 s 15,6 s 15,6 s 7,8 s 7,8 s 7,8 s Semiconductor Group 2 Preliminary Information The HYS72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 8M x 72, 16M x 72, 32M x 72, 64M x 72 & 128M x 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. The 256MB module is available as one bank and two bank module version. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint. Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS DQMB4 DQMB5 NC RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 A12 PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC Semiconductor Group 3 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules RCS0 RDQMB0 DQ(7:0) CS DQM DQ0-DQ7 D0 CS RDQMB1 DQ(15:8) DQM DQ0-DQ7 D1 CS WE DQM RCB(7:0) RCS2 RDQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS RDQMB3 DQ(31:24) VCC C VSS D0 - D8, Reg., DLL SA0 SA1 SA2 SCL Notes: 1.) DQ wiring may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ohm unless otherwise noted *) A12 is only used for 32M x 72 organisation CS RDQMB4 DQ(39:32) DQM DQ0-DQ7 D4 CS RDQMB5 DQ(47:40) DQM DQ0-DQ7 D5 DQ0-DQ7 D8 CS RDQMB6 DQ(55:48) DQM DQ0-DQ7 D6 CS RDQMB7 DQ(63:56) D3 DQM DQ0-DQ7 D7 E2PROM (256wordx8bit) SA0 SA1 SA2 SCL DQM DQ0-DQ7 D0 - D8, Reg., DLL SDA WP 47k CLK0 20pF PLL SDRAMs D0-D8 CS0/CS2 DQMB0-7 BA0,BA1 A0-11,12*) RAS CAS CKE0 WE Vcc REGE 10k RCS0/RCS2 RDQMB0-7 RBA0,RBA1 RA0-11,12 RRAS RCAS RCKE0 RWE SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 Register CLK1,CLK2,CLK3 30pF Block Diagram for one bank 8M x 72 & 32M x 72 SDRAM DIMM modules HYS72V8200GR / HYS72V32200GR using x8 organised SDRAMs Semiconductor Group 4 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules RCS0 RDQMB0 DQM CS DQ0-DQ3 DQ0-DQ3 DQM CS DQ4-DQ7 RDQMB1 DQM CS DQ8-DQ11 DQ0-DQ3 DQM CS DQ12-DQ15 DQ0-DQ3 DQM CS CB0-CB3 RCS2 RDQMB2 DQM CS DQ16-DQ19 DQ0-DQ3 DQM CS DQ20-DQ23 RDQMB3 DQM CS DQ24-DQ27 DQ0-DQ3 DQM CS DQ28-DQ31 CLK0 20pF RDQMB4 DQ32-DQ35 DQM CS DQ0-DQ3 DQM CS D8 D0 DQ0-DQ3 DQ36-DQ39 D1 RDQMB5 DQ0-DQ3 DQM CS D9 D2 DQ40-DQ43 DQ0-DQ3 DQM CS D10 D3 DQ44-DQ47 DQ0-DQ3 DQM CS D11 DQ0-DQ3 D16 CB4-CB7 RDQMB6 DQ48-DQ51 DQ0-DQ3 D17 DQM CS DQ0-DQ3 DQM CS D12 D4 DQ52-DQ55 D5 RDQMB7 DQM CS D6 DQ56-DQ59 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 D13 D14 DQM CS WE D7 DQ61-DQ63 DQ0-DQ3 D15 DQ0-DQ3 PLL SDRAMs D0-D17 CLK1,CLK2,CLK3 RCS0/RCS2 RDQMB0-7 RBA0,RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE 30pF CS0/CS2 DQMB0-7 BA0,BA1 A0-A11,A12*) RAS CAS CKE0 WE 10k SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 E2PROM (256wordx8bit) SA0 SA0 SDA SA1 SA1 SA2 WP SA2 SCL SCL 47k VCC C VSS D0 - D17, Reg.,DLL 1.) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ohm unless otherwise noted *) A12 is only used for 64M x 72 organisation Register D0 - D17, Reg. DLL Vcc REGE Block Diagram for one bank 16M x 72 & 64M x 72 SDRAM DIMM modules HYS72V16200GR / HYS72V64200GR using x4 organised SDRAMs Semiconductor Group 5 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules RCS0 RCS1 RDQMB0 DQM CS DQ0-DQ3 DQM CS DQ0-DQ3 DQ0-DQ3 D0 D0 DQM CS DQ4-DQ7 RDQMB1 DQ8-DQ11 DQM CS DQ0-DQ3 DQ0-DQ3 D1 D1 DQM CS DQM CS RDQMB4 DQ32-DQ35 DQM CS DQ36-DQ39 RDQMB5 DQM CS DQ40-DQ43 DQM CS DQ0-DQ3 DQ0-DQ3 D9 D9 DQM CS DQ0-DQ3 DQ0-DQ3 D2 D2 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D3 D3 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D16 D16 DQ0-DQ3 DQ0-DQ3 D10 D10 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D11 D11 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D17 D17 DQ12-DQ15 DQ44-DQ47 CB0-CB3 RCS2 RCS3 RDQMB2 DQ16-DQ19 CB4-CB7 DQM CS DQM CS RDQMB6 DQ48-DQ51 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D4 D4 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D5 D5 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D12 D12 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D13 D13 DQM CS DQM CS DQ20-DQ23 RDQMB3 DQ24-DQ27 DQ52-DQ55 RDQMB7 DQ56-DQ59 DQ0-DQ3 DQ0-DQ3 D6 D6 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D7 D7 PLL stacked SDRAMs D0-D17 CLK1,CLK2,CLK3 RCS0/RCS2 RDQMB0-7 RBA0,RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE DQ0-DQ3 DQ0-DQ3 D14 D14 DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D15 D15 DQ28-DQ31 CLK0 20pF DQ61-DQ63 CS0-CS3 DQMB0-7 BA0,BA1 A0-A11,A12* RAS CAS CKE0 WE 10k E2PROM (256wordx8bit) SA0 SA0 SA1 SDA SA1 SA2 WP SA2 SCL SCL 47k stacked SDRAMs D0-D17 stacked SDRAMs D0-D17 stacked SDRAMs D0-D17 VCC D0 - D17, Reg. DLL stacked SDRAMs D0-D17 C stacked SDRAMs D0-D17 VSS D0 - D17, Reg.,DLL stacked SDRAMs D0-D17 30pF 1.) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ohm unless otherwise noted Vcc REGE Register *) A12 is only used for 128M x 72 organisation Block Diagram for two bank 32M x 72 & 128M x 72 SDRAM DIMM modules HYS72V32220GR / HYS72V128220GR using stacked x4 organised SDRAMs Semiconductor Group 6 Preliminary Information DQM CS DQM CS DQ0-DQ3 DQ0-DQ3 D8 D8 Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 10 10 V V V V A A 2.0 - 0.5 2.4 - - 10 - 10 Unit VIH VIL VOH VOL II(L) IO(L) Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Symbol Limit Values (max.) one bank modules two bank modules Unit Input Capacitance (all inputs except CLK) Input Capacitance (CKL) Input / Output capacitance (DQ0-DQ63,CB0-CB7) Input Capacitance (SCL,SA0-2) Input/Output Capacitance (SDA) CIN CCLK CIO Csc Csd 10 30 10 8 10 10 30 15 8 10 pF pF pF pF pF Semiconductor Group 7 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules 64MBit SDRAM Operating Currents (TA = 0 to 70oC, Vdd = 3.3V 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read command cycling tck = min. tck = Infinity tck = min. tck = Infinity CKE>=VIH(min.) CKE<=VIL(max.) Symb. -8/-8B max. Note ICC1 x4 x8 100 110 mA mA 1 ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P 2 1 35 5 45 8 mA mA mA mA mA mA 1 1 1 1 1 1 ICC4 x4 x8 ICC5 60 70 130 mA mA mA 1,2 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V 1 ICC6 1 mA 1 Semiconductor Group 8 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules 256MBit Operating Currents (TA = 0 to 70oC, Vdd = 3.3V 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read command cycling CKE>=VIH(min.) CKE<=VIL(max.) tck = min. tck = min. Symb. -8/-8B max. Note ICC1 x4 x8 210 210 mA mA mA mA 1 ICC2P 2 1 ICC2N 19 mA 1 ICC3N ICC3P 45 10 mA mA 1 1 ICC4 x4 x8 ICC5 210 210 240 mA mA mA 1,2 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V 1 ICC6 2.5 mA 1 Semiconductor Group 9 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) 3)4) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter Symbol Limit Values -8 min. max. Unit -8B min. max. Clock and Clock Enable Clock Cycle Time CAS Latency = 2 tCK CAS Latency = 3 Clock Frequency CAS Latency = 2 tCK CAS Latency = 3 Access Time from Clock CAS Latency = 2 tAC CAS Latency = 3 Clock High Pulse Width Clock Low Pulse Width Transition time - - 3 3 0.5 6 6 - - 10 - - 3 3 0.5 7 6 - - 10 ns ns ns ns 4 10 10 - - - - 100 100 12 10 - - - - 83 100 ns MHz tCH tCL tT Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up time Power Down Mode Entry Time tIS tIH tCKS tCKH tRSC tSB 2 1 2 1 16 0 - - - - - 8 2 1 2 1 20 0 - - - - - 10 ns ns ns ns ns ns 5 5 5 5 Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period tRCD tRP tRAS tRC tRRD tCCD 20 20 45 70 16 1 - - 100k 20 30 60 80 20 1 - - 100k ns ns ns ns ns CLK 6 6 6 6 6 - - - - - - Semiconductor Group 10 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Parameter Symbol Limit Values -8 min. max. Unit -8B min. max. Refresh Cycle Refresh Period 64M SDRAM based modules 256M SDRAM based modules Self Refresh Exit Time tREF - - 15,6 7,8 - - 10 15,6 s 7,8 s ns tSREX 10 Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency tOH tLZ tHZ tDQZ 3 0 3 - - - 8 2 3 0 3 - - - 10 2 ns ns ns CLK 8 Write Cycle Data Input to Precharge (write recovery) Data In to Active / Refresh DQM Write Mask Latency tWR tDAL tDQW 2 5 0 - - - 2 5 0 - - - CLK CLK CLK Semiconductor Group 11 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Clock Frequency and Latency (Registed DIMM Module Specification): 9) Parameter Clock Frequency Clock Cycle Time CAS Latency RAS to CAS Delay RAS Latency Precharge Time Data In to Precharge Data In to Active / Refresh Bank to Bank Delay Time CAS to CAS delay time Write Latency DQM Write Mask Latency DQM Data Disable Latency Clock Suspend Latency max. min. min. min. min. min. min. min. min. min. fixed fixed fixed fixed Symbol tCK tCK tAA tRCD tRL tRP tDPL tDAL tRRD tCCD tWL tDQW tDQZ tCSL -8 100 10 3 2 6 2 2 5 2 1 1 1 1 1 -8B 100 10 4 2 7 3 2 5 2 1 1 1 1 1 Unit Notes MHz ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK 10) 10) 10) 10) Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per SDRAM component. 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.). 3. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before any operation can be guaranteed. 4. AC timing tests have Vil = 0.8V and Vih = 2.0V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns Semiconductor Group 12 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules with the AC output load circuit shown. Specified tac and toh parameters are measured with a 50 2.0V CLOCK 0.8V + 1.4 V 50 Ohm tT tSETUP tHOLD Z=50 Ohm I/O 1.4V INPUT 50 pF tAC tLZ tOH tAC I/O 50 pF OUTPUT 1.4V Meaurement conditions for tac and toh tHZ pF only, without any resisitve termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to "wake-up" the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 8. tDAL is equivalent to tDPL + tRP. 9. Due to the usage of a register device on all input and address signals, all external command cycle are delayed by one clock (Reg-DIMM Latency = 1) on the module board. 10. Delayed by one clock cycle due to the use of the register device. Semiconductor Group 13 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules A serial presence detect storage device - E 2PROM 34C02 - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table for -8 Registered DIMM Modules with PLL: Byte# Description SPD Entry Value 64MB with PLL 1 bank Hex 128MB 256MB 256MB with with with PLL PLL PLL 1 bank 2 banks 1 bank 512MB with PLL 1 bank 1GB with PLL 2 bank 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels Cycle Time at CL=3 Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 12 / 13 9 / 10 / 11 1 72 0 LVTTL 10.0 ns 6.0 ns ECC SelfRefresh, 15.6s x4, x8 n/a / x4 1 CLK 1, 2, 4, 8 & full page 4 2&3 0 0 with PLL Vcc tol +/10% 10 ns 6 ns not supported 80 08 04 0C 09 01 48 00 01 A0 60 02 80 80 08 04 0C 0A 01 48 00 01 A0 60 02 80 80 08 04 0C 0A 02 48 00 01 A0 60 02 80 80 08 04 0D 0A 01 48 00 01 A0 60 02 80 80 08 04 0D 0B 01 48 00 01 A0 60 02 80 80 08 04 0D 0B 02 48 00 01 A0 60 02 80 13 14 15 16 17 18 19 20 21 22 23 24 25 SDRAM width, Primary Error Checking SDRAM data width Minimum tCCD Burst Length supported Number of SDRAM banks SDRAM Supported CAS Latencies SDRAM CS Latencies SDRAM WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes Min. Clock Cycle Time at CL = 2 Max. data access time from Clock for CL=2 Min. Clock Cycle Time at CL = 1 08 08 01 8F 04 06 01 01 16 0E A0 60 FF 04 04 01 8F 04 06 01 01 16 0E A0 60 FF 04 04 01 8F 04 06 01 01 16 0E A0 60 FF 08 08 01 8F 04 06 01 01 16 0E A0 60 FF 04 04 01 8F 04 06 01 01 16 0E A0 60 FF 04 04 01 8F 04 06 01 01 16 0E A0 60 FF Semiconductor Group 14 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules SPD cont' Byte# Description SPD Entry Value 64MB with PLL 1 bank Hex 128MB 256MB 256MB with with with PLL PLL PLL 1 bank 2 banks 1 bank 512MB with PLL 1 bank 1GB with PLL 2 bank 26 27 28 29 30 31 32 33 34 35 36-61 Max. Data Access Time from Clock at CL=1 SDRAM Minimum tRP SDRAM Minimum tRRD SDRAM Minimum tRCD SDRAM Minimum tRAS Module Bank Density (per bank) not supp. 20 ns 16 ns 20 ns 45 ns 64/128/256/ 512 MByte 2 ns 1 ns 2 ns 1 ns FF 14 10 14 2D 10 20 10 20 10 FF 12 08 FF 14 10 14 2D 20 20 10 20 10 FF 12 11 FF 14 10 14 2D 20 20 10 20 10 FF 12 12 FF 14 10 14 2D 40 20 10 20 10 FF 12 3A FF 14 10 14 2D 80 20 10 20 10 FF 12 73 FF 14 10 14 2D 80 20 10 20 10 FF 12 74 SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 -62 64- Manufacturer's information 125 (FFh it not used) 126 Frequency Specification 127 Details of Clocks 128+ Unused storage locations 1.2 100 Mhz 64 8F 64 8F 64 8F 64 8F 64 8F 64 8F Semiconductor Group 15 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8B Registered DIMM Modules with PLL: Byte# Description SPD Entry Value 64MB with PLL 1 bank Hex 128MB 256MB 256MB with with with PLL PLL PLL 1 bank 2 banks 1 bank 512MB with PLL 1 bank 1GB with PLL 2 bank 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels Cycle Time at CL=3 Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 12 / 13 9 / 10 / 11 1 72 0 LVTTL 10.0 ns 6.0 ns ECC SelfRefresh, 15.6s x4, x8 n/a / x4 1 CLK 1, 2, 4, 8 & full page 4 2&3 0 0 with PLL Vcc tol +/10% 12 ns 7 ns not supported 80 08 04 0C 09 01 48 00 01 A0 60 02 80 80 08 04 0C 0A 01 48 00 01 A0 60 02 80 80 08 04 0C 0A 02 48 00 01 A0 60 02 80 80 08 04 0D 0A 01 48 00 01 A0 60 02 80 80 08 04 0D 0B 01 48 00 01 A0 60 02 80 80 08 04 0D 0B 02 48 00 01 A0 60 02 80 13 14 15 16 17 18 19 20 21 22 23 24 25 SDRAM width, Primary Error Checking SDRAM data width Minimum tCCD Burst Length supported Number of SDRAM banks SDRAM Supported CAS Latencies SDRAM CS Latencies SDRAM WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes Min. Clock Cycle Time at CL = 2 Max. data access time from Clock for CL=2 Min. Clock Cycle Time at CL = 1 08 08 01 8F 04 06 01 01 16 0E C0 70 FF 04 04 01 8F 04 06 01 01 16 0E C0 70 FF 04 04 01 8F 04 06 01 01 16 0E C0 70 FF 08 08 01 8F 04 06 01 01 16 0E C0 70 FF 04 04 01 8F 04 06 01 01 16 0E C0 70 FF 04 04 01 8F 04 06 01 01 16 0E C0 70 FF Semiconductor Group 16 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules SPD cont' Byte# Description SPD Entry Value 64MB with PLL 1 bank Hex 128MB 256MB 256MB with with with PLL PLL PLL 1 bank 2 banks 1 bank 1GB 512MB with with PLL PLL 1 bank 2 banks 26 27 28 29 30 31 32 33 34 35 36-61 Max. Data Access Time from Clock at CL=1 SDRAM Minimum tRP SDRAM Minimum tRRD SDRAM Minimum tRCD SDRAM Minimum tRAS Module Bank Density (per bank) not supp. 30 ns 20 ns 20 ns 60 ns 64/128/256/ 512 MByte 2 ns 1 ns 2 ns 1 ns FF 1E 14 14 3C 10 20 10 20 10 FF 12 55 FF 1E 14 14 3C 20 20 10 20 10 FF 12 5E FF 1E 14 14 3C 20 20 10 20 10 FF 12 57 FF 1E 14 14 3C 40 20 10 20 10 FF 12 87 FF 1E 14 14 3C 80 20 10 20 10 FF 12 C0 FF 1E 14 14 3C 80 20 10 20 10 FF 12 C1 SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 -62 64- Manufacturer's information 125 (FFh it not used) 126 Frequency Specification 127 Details of Clocks 128+ Unused storage locations 1.2 100 Mhz 64 8D 64 8D 64 8D 64 8D 64 8D 64 8D Semiconductor Group 17 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Module Package JEDEC MO-161 64 & 256 MByte Registered DIMM Module 133,35 127,35 4,0 Register Register 1 10 11 42,18 66,68 A B 40 41 84 1,27+ 0.1 C 85 94 95 124 125 PLL 168 6,35 3,125 3,125 6,35 1,27 2,54 min. 1,0 + 0.5 - 2,0 Detail A Detail B 2,0 Detail C DM168-R1.WMF preliminary drawing Semiconductor Group 18 Preliminary Information 17,78 38,10 3,0 Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Module Package JEDEC MO-161 128 & 512 MByte Registered DIMM Module 133,35 127,35 4,0 PLL 1 10 11 42,18 66,68 A B C 40 41 84 1,27+ 0.1 - 85 94 95 124 125 Register Register 168 6,35 3,125 3,125 6,35 1,27 2,54 min. 1,0 + 0.5 - 2,0 Detail A Detail B 2,0 Detail C DM168-R2.WMF preliminary drawing Semiconductor Group 19 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules 17,78 43,18 3,0 Module Package JEDEC MO-161 256 MByte & 1GByte Registered DIMM Module with stacked SDRAMs 133,35 127,35 4,0 PLL 1 10 11 42,18 66,68 A B C 40 41 84 1,27+ 0.1 - 85 94 95 124 125 Register Register 168 6,35 3,125 3,125 6,35 1,27 2,54 min. 1,0 + 0.5 - 2,0 Detail A Detail B 2,0 Detail C DM168-R3.WMF preliminary drawing Semiconductor Group 20 Preliminary Information 17,78 43,18 3,0 Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules Functional Description All 168 Pin Registered DIMMs conform to a compatible set of timing and operation characteristics intended to comply with the 100 MHz standards. The Registered DIMMs achieve high speed data transfer rate up to 100 MHz. All control and address signals are synchronized with the positive edge of externally supplied clocks and are registerd on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM devices. The use of the on-board register reduces the capacitive loading of the DIMM on input controll and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show DIMM operation at the tabs, not SDRAM operation. The picture below depicts an overview of the effect of the Registered Mode on the data outputs (DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS latency, in the case two clocks. With the register, the data is delayed according to the device CAS latency plus an additional clock cycle. This is know as the DIMM CAS latency, and in this example is four three. The data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. Registered DIMM Burst Read Operation (BL=4) T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ A NOP NOP NOP NOP NOP NOP Device CAS latency = 2 tCK2, DQ's DIMM CAS latency = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 tCK3, DQ's one clock DOUT A0 DOUT A1 DOUT A2 DOUT A3 added for on-DIMM pipeline register Reg-DIMM Latency = 1 Semiconductor Group 21 Preliminary Information Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP DQ's DIN A0 DIN A1 DIN A2 DIN A3 don't care The first data element and the Write are registered on the next clock edge Reg-DIMM Latency = 1 CLK Extra data is ignored after termination of a Burst. Semiconductor Group 22 Preliminary Information In case of a Burst Write Command the data-in is delayed one clock due th the op-DIMM pipeline register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the next clock cycle after the Write command is issued. the remainig data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Rev. 1.0/1.1 HYS72Vx2x0GR Registered SDRAM-Modules |
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